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02/23/2011
Fault tolerant system - ongoing research project at ESRG laboratory.
 
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Low-Power Reconfigurable Fault-tolerant Platforms

 

Introduction

Embedded Systems (ESs) represent the major market of microprocessors. Recently there has been a definite tendency to utilize ESs in real time applications in which high performance and re-configurability, fault tolerance and reduced energy consumption are desirable. Within the framework of this project efficient solving of the three problems will be in focus of interest. Since field programmable gate arrays (FPGAs) were introduced there have radically changed the way digital logic is designed and deployed. FPGAs have made possible to use in numerous embedded applications. The first main goal of this project is to make designers comfortable with these issues, and able to exploit a vast opportunity that offers the reconfigurable logic. Modern ES architectures present new challenges to fault tolerant (FT) design engineers. Much previous work in FT hardware design focused on gate-level approaches, but now more work is needed at much higher level of abstraction, making complete design validation more difficult. The second goal this project is to prepare design engineers how to set trade-off point between fault tolerance, performance, and low power consumption. Today, the power consumption of ESs is considered as one of the most important problems for portable devices. This is due to the limited cell battery lifetime. The third goal of this project is to navigate researchers towards design of efficient power management and energy harvesting circuitries implemented in ES devices.

Applications

ESs are a combination of hardware and software parts, as well as other components that are bring together into products such as cell phone, a music player, a network router, etc. They are systems within another system. ESs techniques allow us to make products that are smaller, faster, more flexible, more reliable, and cheaper. VLSI ICs are the key component in enabling all this to happen. Before two decades, we talked about tens of transistors. Yesterday we discussed in terms of millions of transistors collected into a single IC. Today, the industry began to embrace new design with billion of transistors and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. Without VLSI the SoC designs would be not feasible, and without ESs, SoC designs would serve little purpose.

Although ESs have been in use for decades, in the last few years there has been a definite tendency to utilize them in more real-time complex applications in which more total computing power, fault tolerance, and reduced energy consumption are desirable.

What are our goals

SoC design is the ultimate challenge of the semiconductor industry. It involves the creation of complex VLSI ICs that contain from hundred of millions up to billion of transistors fabricated on nanoscale technology, performing all (or nearly all) of the functionality of a complete end-uses embedded application. This funcionality must be achieved at high-computing performance, high architectural flexibility, high reliability, at the lowest possible power consumption, as rapidly as possible, and at the lowest possible development cost and unit price.

Almost all ES SoCs are build around general purpose procesor, digital signal processor and several specialized IP cores, and thus have significiant software content that often requires at least as much development effort as the hardware architecture. Creation of software for SoC design is our main interest. Several strategic goals is necessary to achieve during realization of this project. Thay are the following:

1. As we move to the era of multi-million gate VLSI ICs it has become to adopt new design methodology based on reuse strategies for these complex SoCs. To this end we plan first to educate a group of young researchers capable to be familiar with contemporary design tools, especially in the following fields: a) extensive re-use of hardware and software IP cores; b) design flow that maximizes parallel hardware/software (HW/SW) development; c) design flow that enables at-speed verification of HW/SW before prototype fabrication; d) design methodology that gives rapid time-to-market end user application, while optimizing performance, reliability, and power consumption.

2. The outputs of the project should be products in a form of: i) soft IP cores intended as accelerators in DSP industrial and medical applications; ii) reconfigurable fault tolerant logic in SoC; iii) power management and energy harvesting blocks. Our intent is to make products that will be attractive and competitive both at domestic, neighbouring, and markets of EU.

3. We plan to use the achieved results in the following areas:

a) Soft IP cores as accelerators components in different types of SoC designs.

b) Fault-tolerant chip architectures for automotive, industrial, and medical safety critical applications.

c) The energy management and energy harvester module should be unavoidable constituent of each low or ultra-low power ES battery powered portable devices such as for example, sensor nodes within the wireless sensor network, medical implants, etc.

4. Rising of knowledge level of our master and PhD students in the field of SoC design, in general, and design of soft IP cores as accelerator bloces, safety-critical single-chip fault to tolerant platforms, and power supply units (dynamic power manager and harvesting modules) in particular. Accordingly one PhD and several master thesis arre planned for this project.

5. Finally, results dissemination in a form of presentation of results that have a positive echo in the world will be conducted. Namely, we plan to publish several papers in eminent international journals and present the achieved results at international conferences.


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