ESRG Embedded Systems Research Group


Laboratory Manual for Microprocessor Systems

Tatjana Stankovic, Sasa Ristic, Milos Krstic, Ivan Andrejic and Mile Stojcev

Cover page and Intro page
(click on a image for larger photo)
Authors Assistant Tatjana Stankovic, Assistant Sasa Ristic, Assistant Milos Krstic, Assistant Ivan Andrejic, and Prof. dr Mile Stojcev, University of Nis
Title Laboratory Manual for Microprocessor Systems
Publisher Faculty of Electronic Engineering, Nis
Year 2004
ISBN 86-80135-82-8
COBISS-ID 112536076
Reviewers Assistant Prof.. dr Goran Djordjevic, University of Nis
Associated Prof. dr Ivan Milentijevic, University of Nis
Pages XI + 221
Illustrations 54 Figures and 6 Tables
Language Serbian
Type Text-Book
Categorization Computer Architecture / Microprocessor Systems / Lab Exercises
Abstract This book contains a set of lab exercises used in teaching the assembly languages of MIPS processor and Intel 80x86 family of processors, and logic design and verification of one three stages pipeline processors. These exercises are already introduced at Faculty of Electronic Engineering in Nis, University of Nis, Faculty of Electrical Engineering Srpsko Sarajevo, University of Pale (Bosnia and Herzegovina), and should be introduced at Faculty of Science and Mathematics in Ni?, University of Ni?. In total, 30 exercises are developed. They are divided into four groups.
From the review

The first four exercises are related to basic topics in DOS and the most frequent commands, DEBUG facilities, AUTOEXEC.BAT and CONFIG.SYS files, and batch files. The fifth exercise introduces PWB (Programmer's Work Bench) editor, QuickHelp program offering the help for assembler instructions, and CodeView debugging tool.
The exercises 6-19 are devoted to Intel processor family programming. By completing these exercises, the students become capable to write and run programs for Intel microprocessor family. Now, their knowledge in assembly programming is medium graded, and allows them to be independent in future programming tasks. Moreover, they should understand better the architecture of computers based on Intel microprocessor family, and they should know more about overall computer operation.
The exercises 20-26 deal with MIPS programming and the corresponding simulator. MIPS processors are typical representatives of RISC architecture. We use PCSpim simulator to simulate such architecture. Using PCSpim simulator and MIPS assembly language in these exercises, the students, beside of skills in MIPS programming, get better picture about RISC architecture and parallelism on machine and instruction level.
The exercises 27 - 30 are devoted to the VHDL. They cover pipelined microcontroller design. The example microcontroller consists of four blocks: predecode, decode, register file, and execute. Using these exercises, students should get the basic knowledge about logic design in VHDL and pipelined processor organization.





Copyright ESRG June 2005